The present invention related to electrical test probes and more specifically to a high-speed, low-profile logic analyzer test probe having reduced inductive and capacitive loading.
Logic analyzer test probes are specialized types of voltage test probes that are optimized for probing digital and computer boards. Square pins are added to these boards to access logic signals and often have ground pins next to the signal pins for high speed signal acquistion. Instead of having a probing tip as in conventional voltage probes, a logic analyzer probe has a socket connector for mounting the probe on a signal pin. A signal wire leads from the logic analyzer probe to a interface pod, which is coupled to the input channels of the logic analyzer. Depending on the bandwidth requirements of the logic analyzer, passive or active circuitry may be included in the probe. In addition, the probe may contain a ground connection to the device under test to reduce capacitive loading.
FIGS. 1A-D show examples of prior art logic analyzer test probes. The simplest type of logic analyzer probe is shown in FIG. 1A. The probe 10 has a probing head socket connector 12 connected to a length of wire 16, which connected to the interface pod 18. Depending on the design of the logic analyzer, the interface pod 18 may contain circuitry for providing a high input impedance to the device under test (DUT), amplification of the acquired signal, and signal timing. Shrink wrap material 20 is formed over the socket 12 to provide electrical insulation. A second probe 22 is required to provide the ground connection to the DUT. This type of probe is very good for probing tight spaces but has very high inductive and capacitive loading due to the long lead lengths from the probing head 12 to the interface pod 18 and from the ground probe 22 to the probe head 12.
Probes 24 and 26 of FIGS. 1B and 1C partially overcome the inductive and capacitive loading problem of the previous probe 10 by providing high input impedance circuitry in a probe head podlet 28. In addition, the podlets 28 have a molded-in socket 30 for connecting the probes 24 and 26 to the ground of the DUT. The high input impedance circuitry and ground connection of the probes 24 and 26 are encapsulated in an insulating material forming the podlets 28. The podlets 28 are electrically connected to the interface pod 18 via twisted pair wires 34. In use, multiple podlets 28 are connected to the interface pod 18 with the maximum number of podlets being equal to the maximum number of channels for the acquisition circuitry of the logic analyzer.
In probe 24 of FIG. 1B, a wire 36 extends from the podlet 28 to a socket connector 38 which is used for probing the device under test. The wire 36 is connected to the compensating circuitry in the podlet 28. A ground socket 42 and wire 44 are connected to the molded-in ground socket 30 in the podlet 28 for coupling the DUT ground to the probe. While this type of probe has substantially increased bandwidth, inductive and capactive loading is still present due to the wire leads 36 and 44 extending from the podlet 28 to the signal test point and to the DUT ground. In addition, each probe socket 38 and ground socket 42 must be individually placed on test and ground pins of the DUT. With logic analyzers having the capability to receiving data over hundreds of channels at a time, it becomes very time consuming for an operator to individually connect each probe and ground connection to the DUT.
Probe 26 of FIG. 1C overcomes the problems of the previous probe by molding the probing socket 38 in the podlet 28 adjacent to the ground socket 30. This minimizes the inductive and capacitive loading caused by the external wire leads 36 and 44 used in the previous probe. In addition, the form factor of podlet 28 allows multiple podlets to be ganged together to form a multichannel probe 46 as is shown in FIG. 1D. The major drawback to this type of probe is that it designed for use with logic and computer boards that have double rows of test pins on an industry standard of one hundred mil centers. For testing individual pins that may not have an associated ground pin on a one hundred mil center, a lead adapter 48 must be used. This results in a probe having the same inductive and capacitive loading as the previous probe.
As can be seen, there are trade-offs in the design of current logic analyzer probes. To maintain ease of use for probing individual test pins of a DUT, sacrifices have to be made with regard to inductive and capacitive loading as well as multichannel probing. To minimize inductive and capacitive loading and provide multichannel probing, sacrifices have to be made with regard to the ease of use in probing individual pins. What is needed is a logic analyzer probe that has the ease of use of probes designed for probing individual pins on a device under test while at the same time minimizing inductive and capacitive loading and providing multichannel probing of a device under test.